1. Field of the Invention
The present invention relates generally to a divide-add circuit and a high-resolution digital-to-analog converter using the same and, more particularly, to a divide-add circuit, which is implemented using only capacitors and switches, and allows an input digital code to be divided into small-bit segments and then be processed at the time of converting a digital signal into an analog signal, thus being capable of implementing a high-resolution digital-to-analog converter, and a high-resolution digital-to-analog converter using the divide-add circuit.
2. Description of the Related Art
When a Digital-to-Analog Converter (hereinafter referred to as a “DAC”) for converting digital signals to analog signals is implemented, performance criteria to be considered includes resolution, accuracy, power consumption, the area of circuitry, conversion speed, etc.
In order to improve the respective performance criteria, various types of DACs have been proposed. In the case where a DAC is necessary as part of a certain integrated system, it is especially important to reduce the area of circuitry and power consumption of the DAC.
A conventional DAC, having the lowest relative complexity, is illustrated in FIG. 1.
The DAC, which is called an algorithmic DAC or a cyclic DAC, includes two capacitors C1 and C2 having the same value, a plurality of switches S1 to S3 for controlling the charging and discharging of the capacitors C1 and C2, and a switch S4 for initializing circuitry.
In the conventional DAC, the switch S4 is turned on and causes an output voltage Vda to drop to 0 V, prior to the start of conversion.
Thereafter, the switch S1 or the switch S2 is turned on depending on the value of a charging and discharging control signal and the value of a digital signal desired to be converted. The switch S3 is turned on when the switches S1 and S2 are turned off, and the switch S1 or S2 is turned on when the switch S3 is turned off again. Such a process is repeatedly performed from the Least Significant Bit (LSB) of an input digital code to the Most Significant Bit (MSB) thereof.
That is, the switch S4 is turned on and the output voltage Vda is initialized. Thereafter, when the value “1” of the LSB of the input digital code is input, the switch S1 is turned on, and the switches S2 and S3 are in an OFF-state. In this case, the capacitor C1 is charged to an input voltage Vref.
Thereafter, when the switch S1 is turned off and the switch S3 is turned on, a part of charges, which have been stored in the capacitor C1, are stored in capacitor C2, so that the capacitors C1 and C2 are in a uniform state. That is, the switch S3 plays a role of averaging the voltages of the capacitors C1 and C2.
Thereafter, the switch S3 is turned off again, and the switches S1 and S2 are selectively turned on depending on the value of the input digital code. When the value of the input digital code is “0”, the switch S2 is turned on and the switch S1 is in an OFF-state. In this case, the capacitor C1 is discharged to 0 V.
When the process is repeatedly performed to the MSB of the input digital code, the output voltage Vda is output as an analog voltage corresponding to the input digital code output (refer to FIG. 2)
One of the considerations at the time of design of the above-described DAC is the match between the two capacitors. An error occurs if the values of the two capacitors do not exactly coincide with each other. The error, which occurs due to the mismatch between the capacitors, is greatly affected by the accuracy of a process and, in particular, it is difficult to acquire an exact match between the capacitors in a case where an inexpensive digital process is used.
Furthermore, switching noise error, due to charge injection, occurs when the switches are turned off and charges that have been stored in the capacitors flow into neighboring nodes. Such error seriously affects the accuracy of the above-described DAC.
The conventional DAC described above, such as an algorithmic DAC or a cyclic DAC, is advantageous in that the area thereof is small, and the power consumption thereof is very low. However, the conventional DAC is problematic in that it is difficult to implement a high resolution of, more than eight bits using a recent low-voltage process due to various error factors.